Sample rate converter
US7724861B2 · kind B2 · utility
1Cited by
39References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2006 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Feb 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0628
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for determining a clock rate of a digital phase lock loop is disclosed. The system includes a first input to receive a first clock signal, an output to provide a second clock signal, and a dividerless initial clock rate determination module to calculate an initial clock rate value based on an reciprocal of a pulse length of the first clock signal. In a particular embodiment, the dividerless initial clock rate determination module performs a piecewise linear operation to calculate the initial clock rate value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.