Minimum processor instruction for implementing weighted fair queuing and other priority queuing
US7725513B2 · kind B2 · utility
1Cited by
12References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Dec 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.