Method and apparatus for computing matrix transformations
US7725521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2003 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jul 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing matrix transformations including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two rows of content byte elements are shuffled to generate a first and second packed data respectively including elements of a first two columns and of a second two columns. A third packed data including sums of products is generated from the first packed data and elements from two rows of a matrix by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements from two more rows of the matrix by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed to generate two rows of a product matrix. Elements of the product matrix may be generated in an order that further facilitates a second matrix multiplication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.