System and method for cryptography processing units and multiplier
US7725624B2 · kind B2 · utility
19Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Feb 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.