Methods and apparatus for generating system management interrupts
US7725637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | May 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.