Memory array structure and single instruction multiple data processor including the same and methods thereof
US7725641B2 · kind B2 · utility
3Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.