Pipeline interposer
US7725680B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jul 14, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An application specific integrated circuit (ASIC) comprises a first bus that communicates with inputs and outputs of N processing modules, where N is an integer greater than 1. A control module communicates with the first bus and a second bus that is different than the first bus, and that generates first control signals. A routing module communicates with the first bus, receives data via the second bus from a first memory, selectively routes the data to a first of the inputs, and selectively routes one of the outputs to a second of the inputs. The routing module selects the first and second of the inputs based on the first control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.