Register file bypass with optional results storage and separate predication register file in a VLIW processor
US7725687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jul 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.