Method and apparatus for accelerating processing of a non-sequential instruction stream on a processor with multiple compute units
US7725691B2 · kind B2 · utility
6Cited by
9References
33Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 28, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jun 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including an index section and a compute section; applying the index section to localized data stored in each compute unit to select one of a plurality of stored local parameter sets; and applying in each compute unit the selected set of parameters to the local data according to the compute section to produce each compute unit's localized solution to the generic instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.