Method for generating programmable data rate from a single clock
US7725756B2 · kind B2 · utility
0Cited by
4References
16Claims
0Family size
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Key dates
| Filing date | Jan 4, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Feb 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a wide range of clock rates from a single clock. A delta is generated from a first clock signal and a second clock signal. An accumulative offset is generated from adding the delta to a previous accumulative offset for each clock period of the first clock signal. Whenever an overflow is encountered, the value of the accumulative offset is truncated. The second clock signal is interpolated between adjacent values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.