System and method of managing clock speed in an electronic device
US7725759B2 · kind B2 · utility
2Cited by
44References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input from at least one of the plurality of master devices. The input can be a request an increase to the clock frequency of the bus. Further, the method includes selectively increasing the clock frequency of the bus in response to the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.