Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels
US7725802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2005 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Sep 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/0413
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality (M) of parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each of the parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses offset from the parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the parallel accumulation engines, increasing a parity bit address for each member of the second set of parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.