Method for radiation tolerance by implant well notching
US7725870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2007 |
| Grant date | May 25, 2010 |
| Priority date | — |
| Expiry date | Jun 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.