Method for fabricating an electronic component embedded substrate
US7727802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2005 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Mar 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4644
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an electronic component embedded substrate including an electronic component that is embedded within a buildup layer is disclosed. The method includes a first buildup layer lamination step of laminating plural first buildup layers on a core substrate such that the total thickness of the first buildup layers corresponds to the thickness of the electronic component; a cavity formation step of forming a cavity for accommodating the electronic component at the laminated first buildup layers; an accommodating step of accommodating the electronic component within the cavity; and a second buildup layer lamination step of laminating a second buildup layer on the first buildup layers and the electronic component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.