Reduction of punch-thru defects in damascene processing
US7727885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2006 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Dec 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02282
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.