Clock signal synchronizing device with inherent duty-cycle correction capability

US7728636B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Wolfgang Anton Spirkl · Germering, DE
• Martin Brox · Munich, DE
• Holger Steffens · Herrsching am Ammersee, DE

Key dates

• Filing date: Aug 14, 2007
• Grant date: Jun 1, 2010
• Expiry date: Dec 21, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/0814
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator. The phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to …