Method and circuit for implementing enhanced eFuse sense circuit
US7729188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2008 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Nov 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.