Memory device, memory controller and memory system
US7729200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jul 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.