Systems and methods for frame synchronization
US7729386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jul 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0608
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for detecting framing data in a telecommunications signal. In one embodiment, a frame synchronizer circuit is provided that includes an interface for receiving bits of a telecommunications signal and storage for storing a framing state for the bit positions in the frame, the framing state for a given bit position indicating whether that bit position is a potential holder of the frame synchronization pattern. The frame synchronizer circuit also contains a state update function that determines the current-state for each bit position based on the bit position's previous state, and the value of the most recently received bit in that bit position. The encoding scheme makes use of shorter bit length symbols to represent statistically more frequently occurring states. In one embodiment, a single code word is used to record the state of a sequence of consecutively occurring bit positions that share the same state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.