Low latency video decoder with high-quality, variable scaling and minimal frame buffer memory
US7729421B2 · kind B2 · utility
14Cited by
15References
9Claims
0Family size
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Key dates
| Filing date | Feb 20, 2002 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jan 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/440263
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Loss of decoding time prior to the vertical synchronization signal when motion video is arbitrarily scaled and positioned by placing the frame switch point at the completion of frame decoding and synchronizing the bottom border of the scaled image therewith while maintaining low latency of decoded data. High latency operation is provided only when necessitated by minimal spill buffer capacity and in combination with fractional image size reduction in the decoding path in order to maintain image resolution without requiring additional memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.