Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US7730282B2 · kind B2 · utility
12Cited by
18References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Mar 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.