Pipelined instruction processor with data bypassing and disabling circuit
US7730284B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2004 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | May 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.