Software assisted nested hardware transactions
US7730286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Apr 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for efficiently executing nested transactions is herein described. Hardware support for execution of transactions is provided. Additionally, through the use of logging previous values immediately before a current nested transaction in a local memory and storage of a stack of handlers associated with a hierarchy of transactions, nested transactions are potentially efficiently executed. Upon a failure, abort, or invalidating event/access within a nested transaction, the state of variables or memory locations written to during execution of the nested transaction are rolled-back to immediately before the nested transaction, instead of all the way back to an original state of the variables or memory locations before an enclosing transaction. As a result, nested transactions may be re-executed within enclosing transactions, without flattening the enclosing and nested transactions to re-execute everything.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.