Aggregation of error messaging in multifunction PCI express devices
US7730361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Jul 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several functions share a common PCIe interface logic. A predetermined number of function entities with logical gates, connected in daisy chain configuration, process incoming information, and a decision is made whether each function entity will generate a blocking control or a pass-through control. The error messages are aggregated across the function entities in a single clock cycle with the help of an error controller. The functions can be from IEEE 1394 interface, graphics display controller, sound card, PCIe switch, or PCIe to PCI bridge connection. Each function preferably has a different configuration and security level setting for error reporting and messaging. There may be a plurality of parallel daisy chains, and the PCIe device may include three layers namely, a physical layer, data link layer and transaction protocol layer (for error logging, reporting).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.