Test data compression method for system-on-chip using linear-feedback shift register reseeding
US7730373B2 · kind B2 · utility
1Cited by
3References
18Claims
0Family size
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Key dates
| Filing date | Aug 15, 2007 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Oct 14, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.