Layered decoding of low density parity check (LDPC) codes
US7730377B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2005 |
| Grant date | Jun 1, 2010 |
| Priority date | — |
| Expiry date | Aug 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. The system also comprises a plurality of parity check update modules (PCUMs) in parallel with each other, coupled to the first adder module and adapted to update the check node value estimate, and a second adder module coupled to the plurality of PCUMs and adapted to update the probability value estimate using the extrinsic estimate and the updated check node value estimate. The PCUMs process at least some columns of at least some rows of the parity check matrix in a serial fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.