Method for shielding integrated circuits
US7732321B2 · kind B2 · utility
1Cited by
25References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 4, 2005 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Jul 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for adding an additional layer to an integrated circuit, the method including providing an integrated circuit having an interconnect layer, depositing, over substantially all of an exposed surface of the integrated circuit, an additional layer of material whose conductivity can be altered, and selectively altering the conductivity of a first portion of the additional layer by selective annealing, to produce a sub-circuit in the additional layer, the sub-circuit being in operative electrical communication with the integrated circuit. Related apparatus and methods are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.