Structure and method for forming a planar schottky contact
US7732842B2 · kind B2 · utility
7Cited by
3References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 11, 2007 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Dec 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
Abstract
A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.