Charge-trap type non-volatile memory devices and related methods
US7732856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Jul 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. Related structures are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.