Substrate testing circuit
US7733115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | May 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a substrate testing circuit comprising a testing bus and a testing signal terminal connected to the testing bus, a signal line to be tested in the substrate being connected to the testing bus via a signal connecting terminal, wherein a plurality of signal access terminals are provided on the testing bus; one testing branch is connected between each the signal access terminal and the testing signal terminal; and resistance values of the testing branches are the same. By means of the present invention, since a plurality of signal access terminals are introduced and the testing branches with the same resistance are added so that input resistances and impedances of testing signals across the display screen are substantially identical without making changes to process flow and device hardware structure, input resistances and impedances of respective signal lines are well averaged, thereby no obvious regional attenuation occurs in the testing signals within the pixel area to be tested irrespective of limitation in size of panel, so as to realize tests for panels with greater sizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.