Operating clock generation system and method for audio applications
US7733151B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Dec 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.