Sample and hold circuit for a current mode pipelined analog-to-digital converter
US7733254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Jun 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.