Controlling global bit line pre-charge time for high speed eDRAM
US7733724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Jan 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.