Low power display refresh
US7734943B2 · kind B2 · utility
10Cited by
11References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2003 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Jun 8, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.