Methods, architectures, circuits and systems for transmission error determination
US7734965B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 2008 |
| Grant date | Jun 8, 2010 |
| Priority date | — |
| Expiry date | Apr 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6516
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.