Patent · US Active

Method and system for creating a boolean model of multi-path and multi-strength signals for verification

US7735035B1 · kind B1 · utility

1Cited by

20References

23Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Kei-Yong Khoo · San Jose, US
Mitchell Hines · San Jose, US
Chih-Chang Lin · San Jose, US

Key dates

Filing date	May 31, 2006
Grant date	Jun 8, 2010
Priority date	—
Expiry date	Dec 15, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/3323
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.