Advanced JFET with reliable channel control and method of manufacture
US7736962B1 · kind B1 · utility
9Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | Jan 7, 2009 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A junction field effect transistor comprises an insulating layer formed in a substrate. A source region of a first conductivity type is formed on the insulating layer, and a drain region of the first conductivity type is formed on the insulating layer and spaced apart from the drain region. A channel region of the first conductivity type is located between the source region and the drain region and formed on the insulating layer. A gate region of the second conductivity type surrounds all surfaces of a length of the channel region such that the channel region is embedded within the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.