Method and structure of an one time programmable memory device in an embedded EEPROM
US7736967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Feb 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
Abstract
A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first OTP-EPROM gate overlying the gate dielectric layer in a first cell region, and an EEPROM floating gate and a select gate overlying the gate dielectric layer in a second cell region. An insulating layer is overlying the first OTP-EPROM gate, the EEPROM floating gate and the select gate. An OTP-EPROM control gate is overlying the insulating layer and coupled to the first OTP-EPROM gate. An EEPROM control gate is overlying the insulating layer and coupled to the EEPROM floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.