Semiconductor integrated circuit device
US7737472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.