Trench gate field effect devices
US7737491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Oct 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
Abstract
The present invention relates to a technique for reducing the on-voltage of the semiconductor device by increasing the concentration of minority carriers in the deep region (26) and the intermediate region (28). A semiconductor device according to the invention comprises an electrode, a top region (36) of a second conductivity type connected to the electrode, a deep region of the second conductivity type, and an intermediate region of a first conductivity type connected to the electrode. A portion of the intermediate region isolates the top region and the deep region. The semiconductor device further comprises a gate electrode (32) facing the portion of the intermediate region via an insulating layer. The portion facing the gate electrode isolates the top region and the deep region. The semiconductor device according to the invention further comprises a barrier region (40) that is formed within the intermediate region and/or the top region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.