Total ionizing dose suppression transistor architecture
US7737535B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jul 16, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/953
Abstract
A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.