Stacked semiconductor devices and signal distribution methods thereof
US7737540B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 7, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jul 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.