Stackable semiconductor package and method for its fabrication
US7737565B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Sep 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stackable semiconductor package includes a board having first electrical connections, an integrated circuit chip fixed on a front face of the board, second electrical connections which connect the chip to the first electrical connections of the board and front electrical contact terminals arranged beyond at least one edge of the chip on the front face of this board. An encapsulation block of a coating material is formed on the front face of the board and encapsulates the chip, its electrical connections and the front terminals. The block has at least one opening which at least partially uncovers the front terminals with a view to receiving electrical connection beads of a stacked second package. This one opening is preferably in the form of a groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.