Phase-locked loop including sampling phase detector and charge pump with pulse width control
US7737743B1 · kind B1 · utility
49Cited by
2References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Mar 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.