Periphery clock distribution network for a programmable logic device
US7737751B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2007 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution network includes a central periphery clock bus, located near a group of peripheral input/output regions, for conducting clock-type signals from those regions onto a clock spine of the PLD. The clock spine may be dedicated to the signal distribution network, or may be part of a high-quality, low-skew clock distribution network covering all or part of the PLD. The signal distribution network allows greater skew than such high-quality, low-skew clock distribution networks, but nevertheless is of higher quality, and allows less skew, than the general programmable interconnect and routing resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.