Level shift circuit
US7737756B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 22, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jul 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a level shift circuit, even when a power supply voltage of an input signal is reduced, a level shift operation is reliably performed without causing increase in circuit area and process costs. For a pair of n-type transistors which receive an input signal and a reverse signal of the input signal as a pair of complementary signals at their gates, respectively, a layout which allows reduction in unit gate width size is adopted. The layout configuration includes a plurality of divided rectangular doped regions which function as drains and sources and a plurality of gates arranged to align in a gate length direction with a gate width direction according with a short side direction of the doped regions. The gates are electrically connected with one another, the drains are electrically connected with one another, and the sources are electrically connected with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.