Low-noise DC offset calibration circuit and related receiver stage
US7737775B2 · kind B2 · utility
2Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Jul 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0296
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver stage has an operational amplifier, a feedback resistor coupled between an output of the operational amplifier and an input of the operational amplifier, and a DC offset calibration circuit. The DC offset calibration circuit includes a plurality of resistors and a plurality of switches. Each resistor has a first end coupled to a supply voltage. First ends of each of the switches are coupled to second ends of each of the resistors, respectively, and second ends of the switches are coupled to the input of the operational amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.