GPU pipeline multiple level synchronization controller processor and method
US7737983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2006 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Feb 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.