Patent · US Active

Bus architecture and method for exchanging data

US7738477B2 · kind B2 · utility

2Cited by

8References

15Claims

0Family size

Assignee

Diehl Avionik Systeme GmbH · DE

Inventors

Peter Hoche · Schmitten, DE
Stefan Orth · Weil der Stadt, DE

Key dates

Filing date	Jul 13, 2006
Grant date	Jun 15, 2010
Priority date	—
Expiry date	Feb 6, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2012/4028
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A bus architecture has a central processing unit, a data line and bus users. The central processing unit and the bus users are connected to the data line via a bus interface. The data line is constructed as a ring and the central processing unit has two transceiver units which can be switched between transmit and receive modes. The central processing unit provides a clocked emission of data intended for the bus users. The bus users are successively connected to the data line, and each contains a monitoring unit, which is connected to the associated bus interface and is configured for activating a transmit activity of the bus interface only after receiving a synchronization message, and otherwise blocks this activity. In a method for exchanging data with such a bus architecture, a high fault tolerance, particularly when the data line is cut through, and error locating capability are achieved.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.