Sharing a digital phase-locked loop across multiple packet streams
US7738498B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2005 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Apr 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0632
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.